-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "10/20/2021 20:50:14"

-- 
-- Device: Altera EP3C16F484C6 Package FBGA484
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	TrafficLight IS
    PORT (
	i_sys_clk : IN std_logic;
	i_sys_emergency : IN std_logic;
	i_sys_rst : IN std_logic;
	o_ew_green : OUT std_logic;
	o_ew_red : OUT std_logic;
	o_ew_tens_a : OUT std_logic;
	o_ew_tens_b : OUT std_logic;
	o_ew_tens_c : OUT std_logic;
	o_ew_tens_d : OUT std_logic;
	o_ew_tens_e : OUT std_logic;
	o_ew_tens_f : OUT std_logic;
	o_ew_tens_g : OUT std_logic;
	o_ew_units_a : OUT std_logic;
	o_ew_units_b : OUT std_logic;
	o_ew_units_c : OUT std_logic;
	o_ew_units_d : OUT std_logic;
	o_ew_units_e : OUT std_logic;
	o_ew_units_f : OUT std_logic;
	o_ew_units_g : OUT std_logic;
	o_ew_yellow : OUT std_logic;
	o_ns_green : OUT std_logic;
	o_ns_red : OUT std_logic;
	o_ns_tens_a : OUT std_logic;
	o_ns_tens_b : OUT std_logic;
	o_ns_tens_c : OUT std_logic;
	o_ns_tens_d : OUT std_logic;
	o_ns_tens_e : OUT std_logic;
	o_ns_tens_f : OUT std_logic;
	o_ns_tens_g : OUT std_logic;
	o_ns_units_a : OUT std_logic;
	o_ns_units_b : OUT std_logic;
	o_ns_units_c : OUT std_logic;
	o_ns_units_d : OUT std_logic;
	o_ns_units_e : OUT std_logic;
	o_ns_units_f : OUT std_logic;
	o_ns_units_g : OUT std_logic;
	o_ns_yellow : OUT std_logic
	);
END TrafficLight;

-- Design Ports Information
-- i_sys_clk	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- i_sys_emergency	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- i_sys_rst	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_green	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_red	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_tens_a	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_tens_b	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_tens_c	=>  Location: PIN_G12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_tens_d	=>  Location: PIN_H13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_tens_e	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_tens_f	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_tens_g	=>  Location: PIN_E11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_units_a	=>  Location: PIN_A15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_units_b	=>  Location: PIN_E14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_units_c	=>  Location: PIN_B14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_units_d	=>  Location: PIN_A14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_units_e	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_units_f	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_units_g	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ew_yellow	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_green	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_red	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_tens_a	=>  Location: PIN_F14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_tens_b	=>  Location: PIN_B17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_tens_c	=>  Location: PIN_A17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_tens_d	=>  Location: PIN_E15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_tens_e	=>  Location: PIN_B16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_tens_f	=>  Location: PIN_A16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_tens_g	=>  Location: PIN_D15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_units_a	=>  Location: PIN_G15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_units_b	=>  Location: PIN_D19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_units_c	=>  Location: PIN_C19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_units_d	=>  Location: PIN_B19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_units_e	=>  Location: PIN_A19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_units_f	=>  Location: PIN_F15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_units_g	=>  Location: PIN_B18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- o_ns_yellow	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF TrafficLight IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_i_sys_clk : std_logic;
SIGNAL ww_i_sys_emergency : std_logic;
SIGNAL ww_i_sys_rst : std_logic;
SIGNAL ww_o_ew_green : std_logic;
SIGNAL ww_o_ew_red : std_logic;
SIGNAL ww_o_ew_tens_a : std_logic;
SIGNAL ww_o_ew_tens_b : std_logic;
SIGNAL ww_o_ew_tens_c : std_logic;
SIGNAL ww_o_ew_tens_d : std_logic;
SIGNAL ww_o_ew_tens_e : std_logic;
SIGNAL ww_o_ew_tens_f : std_logic;
SIGNAL ww_o_ew_tens_g : std_logic;
SIGNAL ww_o_ew_units_a : std_logic;
SIGNAL ww_o_ew_units_b : std_logic;
SIGNAL ww_o_ew_units_c : std_logic;
SIGNAL ww_o_ew_units_d : std_logic;
SIGNAL ww_o_ew_units_e : std_logic;
SIGNAL ww_o_ew_units_f : std_logic;
SIGNAL ww_o_ew_units_g : std_logic;
SIGNAL ww_o_ew_yellow : std_logic;
SIGNAL ww_o_ns_green : std_logic;
SIGNAL ww_o_ns_red : std_logic;
SIGNAL ww_o_ns_tens_a : std_logic;
SIGNAL ww_o_ns_tens_b : std_logic;
SIGNAL ww_o_ns_tens_c : std_logic;
SIGNAL ww_o_ns_tens_d : std_logic;
SIGNAL ww_o_ns_tens_e : std_logic;
SIGNAL ww_o_ns_tens_f : std_logic;
SIGNAL ww_o_ns_tens_g : std_logic;
SIGNAL ww_o_ns_units_a : std_logic;
SIGNAL ww_o_ns_units_b : std_logic;
SIGNAL ww_o_ns_units_c : std_logic;
SIGNAL ww_o_ns_units_d : std_logic;
SIGNAL ww_o_ns_units_e : std_logic;
SIGNAL ww_o_ns_units_f : std_logic;
SIGNAL ww_o_ns_units_g : std_logic;
SIGNAL ww_o_ns_yellow : std_logic;
SIGNAL \i_sys_clk~input_o\ : std_logic;
SIGNAL \i_sys_emergency~input_o\ : std_logic;
SIGNAL \i_sys_rst~input_o\ : std_logic;
SIGNAL \o_ew_green~output_o\ : std_logic;
SIGNAL \o_ew_red~output_o\ : std_logic;
SIGNAL \o_ew_tens_a~output_o\ : std_logic;
SIGNAL \o_ew_tens_b~output_o\ : std_logic;
SIGNAL \o_ew_tens_c~output_o\ : std_logic;
SIGNAL \o_ew_tens_d~output_o\ : std_logic;
SIGNAL \o_ew_tens_e~output_o\ : std_logic;
SIGNAL \o_ew_tens_f~output_o\ : std_logic;
SIGNAL \o_ew_tens_g~output_o\ : std_logic;
SIGNAL \o_ew_units_a~output_o\ : std_logic;
SIGNAL \o_ew_units_b~output_o\ : std_logic;
SIGNAL \o_ew_units_c~output_o\ : std_logic;
SIGNAL \o_ew_units_d~output_o\ : std_logic;
SIGNAL \o_ew_units_e~output_o\ : std_logic;
SIGNAL \o_ew_units_f~output_o\ : std_logic;
SIGNAL \o_ew_units_g~output_o\ : std_logic;
SIGNAL \o_ew_yellow~output_o\ : std_logic;
SIGNAL \o_ns_green~output_o\ : std_logic;
SIGNAL \o_ns_red~output_o\ : std_logic;
SIGNAL \o_ns_tens_a~output_o\ : std_logic;
SIGNAL \o_ns_tens_b~output_o\ : std_logic;
SIGNAL \o_ns_tens_c~output_o\ : std_logic;
SIGNAL \o_ns_tens_d~output_o\ : std_logic;
SIGNAL \o_ns_tens_e~output_o\ : std_logic;
SIGNAL \o_ns_tens_f~output_o\ : std_logic;
SIGNAL \o_ns_tens_g~output_o\ : std_logic;
SIGNAL \o_ns_units_a~output_o\ : std_logic;
SIGNAL \o_ns_units_b~output_o\ : std_logic;
SIGNAL \o_ns_units_c~output_o\ : std_logic;
SIGNAL \o_ns_units_d~output_o\ : std_logic;
SIGNAL \o_ns_units_e~output_o\ : std_logic;
SIGNAL \o_ns_units_f~output_o\ : std_logic;
SIGNAL \o_ns_units_g~output_o\ : std_logic;
SIGNAL \o_ns_yellow~output_o\ : std_logic;

BEGIN

ww_i_sys_clk <= i_sys_clk;
ww_i_sys_emergency <= i_sys_emergency;
ww_i_sys_rst <= i_sys_rst;
o_ew_green <= ww_o_ew_green;
o_ew_red <= ww_o_ew_red;
o_ew_tens_a <= ww_o_ew_tens_a;
o_ew_tens_b <= ww_o_ew_tens_b;
o_ew_tens_c <= ww_o_ew_tens_c;
o_ew_tens_d <= ww_o_ew_tens_d;
o_ew_tens_e <= ww_o_ew_tens_e;
o_ew_tens_f <= ww_o_ew_tens_f;
o_ew_tens_g <= ww_o_ew_tens_g;
o_ew_units_a <= ww_o_ew_units_a;
o_ew_units_b <= ww_o_ew_units_b;
o_ew_units_c <= ww_o_ew_units_c;
o_ew_units_d <= ww_o_ew_units_d;
o_ew_units_e <= ww_o_ew_units_e;
o_ew_units_f <= ww_o_ew_units_f;
o_ew_units_g <= ww_o_ew_units_g;
o_ew_yellow <= ww_o_ew_yellow;
o_ns_green <= ww_o_ns_green;
o_ns_red <= ww_o_ns_red;
o_ns_tens_a <= ww_o_ns_tens_a;
o_ns_tens_b <= ww_o_ns_tens_b;
o_ns_tens_c <= ww_o_ns_tens_c;
o_ns_tens_d <= ww_o_ns_tens_d;
o_ns_tens_e <= ww_o_ns_tens_e;
o_ns_tens_f <= ww_o_ns_tens_f;
o_ns_tens_g <= ww_o_ns_tens_g;
o_ns_units_a <= ww_o_ns_units_a;
o_ns_units_b <= ww_o_ns_units_b;
o_ns_units_c <= ww_o_ns_units_c;
o_ns_units_d <= ww_o_ns_units_d;
o_ns_units_e <= ww_o_ns_units_e;
o_ns_units_f <= ww_o_ns_units_f;
o_ns_units_g <= ww_o_ns_units_g;
o_ns_yellow <= ww_o_ns_yellow;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

-- Location: IOOBUF_X0_Y26_N16
\o_ew_green~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_green~output_o\);

-- Location: IOOBUF_X0_Y27_N16
\o_ew_red~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_red~output_o\);

-- Location: IOOBUF_X26_Y29_N16
\o_ew_tens_a~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_tens_a~output_o\);

-- Location: IOOBUF_X28_Y29_N23
\o_ew_tens_b~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_tens_b~output_o\);

-- Location: IOOBUF_X26_Y29_N9
\o_ew_tens_c~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_tens_c~output_o\);

-- Location: IOOBUF_X28_Y29_N30
\o_ew_tens_d~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_tens_d~output_o\);

-- Location: IOOBUF_X26_Y29_N2
\o_ew_tens_e~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_tens_e~output_o\);

-- Location: IOOBUF_X21_Y29_N30
\o_ew_tens_f~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_tens_f~output_o\);

-- Location: IOOBUF_X21_Y29_N23
\o_ew_tens_g~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_tens_g~output_o\);

-- Location: IOOBUF_X26_Y29_N23
\o_ew_units_a~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_units_a~output_o\);

-- Location: IOOBUF_X28_Y29_N16
\o_ew_units_b~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_units_b~output_o\);

-- Location: IOOBUF_X23_Y29_N30
\o_ew_units_c~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_units_c~output_o\);

-- Location: IOOBUF_X23_Y29_N23
\o_ew_units_d~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_units_d~output_o\);

-- Location: IOOBUF_X23_Y29_N2
\o_ew_units_e~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_units_e~output_o\);

-- Location: IOOBUF_X21_Y29_N9
\o_ew_units_f~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_units_f~output_o\);

-- Location: IOOBUF_X21_Y29_N2
\o_ew_units_g~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_units_g~output_o\);

-- Location: IOOBUF_X0_Y27_N9
\o_ew_yellow~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ew_yellow~output_o\);

-- Location: IOOBUF_X0_Y21_N16
\o_ns_green~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_green~output_o\);

-- Location: IOOBUF_X0_Y24_N16
\o_ns_red~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_red~output_o\);

-- Location: IOOBUF_X37_Y29_N2
\o_ns_tens_a~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_tens_a~output_o\);

-- Location: IOOBUF_X30_Y29_N23
\o_ns_tens_b~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_tens_b~output_o\);

-- Location: IOOBUF_X30_Y29_N16
\o_ns_tens_c~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_tens_c~output_o\);

-- Location: IOOBUF_X30_Y29_N2
\o_ns_tens_d~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_tens_d~output_o\);

-- Location: IOOBUF_X28_Y29_N2
\o_ns_tens_e~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_tens_e~output_o\);

-- Location: IOOBUF_X30_Y29_N30
\o_ns_tens_f~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_tens_f~output_o\);

-- Location: IOOBUF_X32_Y29_N30
\o_ns_tens_g~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_tens_g~output_o\);

-- Location: IOOBUF_X39_Y29_N30
\o_ns_units_a~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_units_a~output_o\);

-- Location: IOOBUF_X37_Y29_N30
\o_ns_units_b~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_units_b~output_o\);

-- Location: IOOBUF_X37_Y29_N23
\o_ns_units_c~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_units_c~output_o\);

-- Location: IOOBUF_X32_Y29_N2
\o_ns_units_d~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_units_d~output_o\);

-- Location: IOOBUF_X32_Y29_N9
\o_ns_units_e~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_units_e~output_o\);

-- Location: IOOBUF_X39_Y29_N16
\o_ns_units_f~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_units_f~output_o\);

-- Location: IOOBUF_X32_Y29_N23
\o_ns_units_g~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_units_g~output_o\);

-- Location: IOOBUF_X0_Y24_N23
\o_ns_yellow~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \o_ns_yellow~output_o\);

-- Location: IOIBUF_X41_Y15_N1
\i_sys_clk~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_i_sys_clk,
	o => \i_sys_clk~input_o\);

-- Location: IOIBUF_X0_Y26_N1
\i_sys_emergency~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_i_sys_emergency,
	o => \i_sys_emergency~input_o\);

-- Location: IOIBUF_X0_Y25_N1
\i_sys_rst~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_i_sys_rst,
	o => \i_sys_rst~input_o\);

ww_o_ew_green <= \o_ew_green~output_o\;

ww_o_ew_red <= \o_ew_red~output_o\;

ww_o_ew_tens_a <= \o_ew_tens_a~output_o\;

ww_o_ew_tens_b <= \o_ew_tens_b~output_o\;

ww_o_ew_tens_c <= \o_ew_tens_c~output_o\;

ww_o_ew_tens_d <= \o_ew_tens_d~output_o\;

ww_o_ew_tens_e <= \o_ew_tens_e~output_o\;

ww_o_ew_tens_f <= \o_ew_tens_f~output_o\;

ww_o_ew_tens_g <= \o_ew_tens_g~output_o\;

ww_o_ew_units_a <= \o_ew_units_a~output_o\;

ww_o_ew_units_b <= \o_ew_units_b~output_o\;

ww_o_ew_units_c <= \o_ew_units_c~output_o\;

ww_o_ew_units_d <= \o_ew_units_d~output_o\;

ww_o_ew_units_e <= \o_ew_units_e~output_o\;

ww_o_ew_units_f <= \o_ew_units_f~output_o\;

ww_o_ew_units_g <= \o_ew_units_g~output_o\;

ww_o_ew_yellow <= \o_ew_yellow~output_o\;

ww_o_ns_green <= \o_ns_green~output_o\;

ww_o_ns_red <= \o_ns_red~output_o\;

ww_o_ns_tens_a <= \o_ns_tens_a~output_o\;

ww_o_ns_tens_b <= \o_ns_tens_b~output_o\;

ww_o_ns_tens_c <= \o_ns_tens_c~output_o\;

ww_o_ns_tens_d <= \o_ns_tens_d~output_o\;

ww_o_ns_tens_e <= \o_ns_tens_e~output_o\;

ww_o_ns_tens_f <= \o_ns_tens_f~output_o\;

ww_o_ns_tens_g <= \o_ns_tens_g~output_o\;

ww_o_ns_units_a <= \o_ns_units_a~output_o\;

ww_o_ns_units_b <= \o_ns_units_b~output_o\;

ww_o_ns_units_c <= \o_ns_units_c~output_o\;

ww_o_ns_units_d <= \o_ns_units_d~output_o\;

ww_o_ns_units_e <= \o_ns_units_e~output_o\;

ww_o_ns_units_f <= \o_ns_units_f~output_o\;

ww_o_ns_units_g <= \o_ns_units_g~output_o\;

ww_o_ns_yellow <= \o_ns_yellow~output_o\;
END structure;


